Digital Engineering

Application of RFSoC Technology within Electronic Warfare aimed against Radar

Digital Engineering
Read time
6 mins
The Challenge

Conceptualising, modelling and implementation of multi-gigahertz sampling system using parallel signal processing architectures.

The Solution

Technical support and services from Opti-Num Solutions and the use of MathWorks’ Pilot Support Package (PSP) for the Xilinx ZCU111 RFSoC Evaluation Kit.

The Results
  • Reduced development time, risk, and cost.
  • Continuous verification and validation during development (improved product quality)
  • Less need for prototypes and physical testing.

The numbers


Decrease in absolute control error


Increase in control performance stability


Increase in throughput Performance


Average increase in flotation level control stability


The Xilinx’s Zynq Ultrascale+ RFSoC technology provides the unique combination of high performance Field-Programmable-Gate-Array (FPGA) resources closely coupled to multiple high-speed data converters in both Analog-to-Digital (ADC) and Digital-to-Analog (DAC) formats, as well as a 64-bit ARM multi-processing system on a single programmable device.  

MathWorks released a Pilot Support Package (PSP) in 2018, for the Xilinx Zynq Ultrascale+ RFSoC ZCU111 Evaluation kit in order to assist system architects and developers to provide a rapid-prototyping solution for Hardware Software Co-Design on the Zynq RFSoC.

Klasie Olivier (Product Manager Radar ESM) worked closely with Praneet Kala (Team Lead at Opti-Num) through technical services and support to speed up development of his R&D project. 


In the domain of Radio Frequency (RF) and Electronic Warfare (EW), instantaneous bandwidth requirements are typically immense. This is especially true in the application area of Radar.

A single Radar emitter can be agile over a wide frequency range. This leads to a very challenging instantaneous bandwidth requirement which typically exceeds 1 GHz for modern Radars.

The RFSoC platform provides the hardware for dealing with complex applications like EW against Radar emitters while MathWorks provides a software development environment which is very capable in supporting signal processing concept development for analysis and evaluation.

One of the major challenges is the parallel signal processing architecture that must be conceptualised, modelled and implemented for multi-Gigahertz sampling systems. It is in this area of parallel signal processing that the HDL Coder Toolbox excels. The design tools embedded within Simulink provide full insight into all aspects of the design through the Logic Analyzer view. 

What We Did

Rapid development time was achieved through the use of Simulink design blocks, together with supporting toolboxes, for the top-level design of the main system developed.  On the top level of the system, a designated block was available that allowed Klasie to design, simulate, and implement his complex FPGA signal processing algorithm. 

The HDL Coder Simulink library provides a rich variety of useful functionality that eases the total design time. Having specific application toolboxes, such as the DSP System Toolbox and Communications Toolbox, provided application specific functional blocks which already directly map to hardware on your target device. He found the FFT functional block within the DSP System Toolbox especially useful since it already supports parallel channel implementation.

Klasie was then able to use this block and auto-generate a Vivado project containing the HDL Coder IP Core, eventually being deployed onto the hardware, in Klasie’s case, on the Xilinx RFSoC FPGA. The generated bitstream was programmed onto the hardware to collect live data from the IP via External Mode from MATLAB running on the host PC. 

This approach allowed for using tried and tested Simulink input blocks into the hardware design under development and then similarly to show outputs of the hardware design under development.  This allowed Klasie to interactively tune parameters or collect information of generated IP at run-time through AXI4 register access from MATLAB/Simulink on a host PC or from Simulink auto-generated embedded C-code.

The Results

Klasie worked mainly with Praneet Kala on his application development and always received very generous support on requests. Even though Klasie’s development work was highly specialised and drawn-out over many months, Praneet put in the hard yards and also brought in MathWorks support directly when it was required.

Klasie was more than satisfied with the level of service received on this advanced demonstration of the concept from Opti-Num Solutions.

  • Simulation environment matches the final implementation one-to-one, this provides very good confidence in measuring on implemented design outputs and then going back to the simulation environment with changes/updates.
  • For solving very complex problems and even more so when you are working on novel concept development, the total HDL design capability within Simulink given all of the application specific toolboxes is exactly what one needs.
  • The last thing a designer needs when attempting to develop towards a new concept is for the tools to be inaccurate or untrusted. This is not the case with the HDL design capability embedded within Simulink.
  • Klasie’s experience using the HDL design capability embedded within Simulink coupled with a Product Support Package for the ZCU111 Xilinx RFSoC evaluation kit provided a development time benefit like nothing else experienced before.

Products Used:

  • Simulink
  • DSP Systems Toolbox
  • Embedded Coder
  • HDL Coder
  • HDL Verifier
  • Stateflow

Hardware Used

  • Xilinx Zynq Ultrascale+ RFSoC ZCU11 Evaluation Kit

Products used
Hardware Used

Grant Grobbelaar

Chief Executive Officer

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